{"id":251299,"date":"2026-07-13T01:10:29","date_gmt":"2026-07-12T22:10:29","guid":{"rendered":"https:\/\/1kitap1.com\/en\/advanced-formal-verification-rolf-drechsler\/"},"modified":"2026-07-13T01:10:29","modified_gmt":"2026-07-12T22:10:29","slug":"advanced-formal-verification-rolf-drechsler","status":"publish","type":"post","link":"https:\/\/1kitap1.com\/en\/advanced-formal-verification-rolf-drechsler\/","title":{"rendered":"Advanced Formal Verification – Rolf Drechsler"},"content":{"rendered":"
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Keim et. al. [24] proved for a certain class of multipliers (unsigned integer Wallace-tree type) that the backward traversal approach is of polynomial space and time complexity. The proof is based on a circuit representation of the multiplier consisting of the AND gates implementing the partial product bits and of full adder cells. Unfortunately, in practice, multiplier netlists are composed of general logic gates and information about the arithmetic sub-components is not available. We experimented with a large number of multipliers generated by our own tools as well as by commercial generators with the goal to im- prove *BMD synthesis by backward traversal as proposed by Hamaguchi.<\/p>\n

However, we were only partially successful. In the following section, we report on these experiments to show where the major problems are. 4.4 Experiments with *BMD synthesis The general intuition behind preferring a backward traversal over a forward traversal is that the former makes better use of the special char- acteristics of *BMDs when representing arithmetic functions.<\/p>\n

Represent- ing a pseudo-Boolean function in the *BMD should always be better than representing a bit-level Boolean function. However, if the network cut is not chosen appropriately, the pseudo-Boolean function implemented by the logic between the cut variables and the (integer) circuit output need not necessarily yield a compact *BMD. The work of [19] suggests a simple topological ordering among the nodes of the circuit when com- posing the *BMD. In our experiments, this node ordering worked well for text-book multipliers generated by our own tool.<\/p>\n

However, for in- dustrial multipliers, we were not able to construct *BMDs using simple topological ordering. In this section we report on a number of experi- ments evaluating where the problems are and how *BMD synthesis could be improved. It has been pointed out by a number of authors [18, 25, 24] that knowledge about the sub-components of a multiplier is very useful in *BMD construction. However, in a gate netlist this information is not available. In order to successfully build a *BMD, however, information about the circuit structure should be exploited.<\/p>\n

The goal is to derive as much information about the internal structure of the gate netlist as possible. As a \ufb01rst improvement over simple topological ordering of nodes to be composed into the *BMD, we experimented with partitioning the gate netlist of a multiplier into non-overlapping cones.<\/p>\n

Each circuit node belongs to exactly one cone.<\/p>\n

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\u00a92004 Kluwer Academic Publishers New York, Boston, Dordrecht, London, Moscow Print \u00a92004 Kluwer Academic Publishers All rights reserved No part of this eBook may be reproduced or transmitted in any form or by any means, electronic, mechanical, recording, or otherwise, without written consent from the Publisher Created in the United States of America Visit Kluwer Online at: http:\/\/kluweronline.com and Kluwer’s eBookstore at: http:\/\/ebooks.kluweronline.com Dordrecht Contents Preface xi Contributing Authors xiii Introduction xix Rolf Drechsler 1 Formal Veri\ufb01cation xix 2 Challenges xxi 3 Contributions to this Book xxiii 1 What Sat-Solvers can and cannot do 1 Eugene Goldberg 1 Introduction 1 2 Hard Equivalence Checking CNF formulas 3 2.1 Introduction 3 2.2 Common Speci\ufb01cation of Boolean Circuits 5 2.3 Equivalence Checking as SAT 11 2.4 Class M(p) and general resolution 12 2.5 Computation of existentially implied functions 13 2.6 Equivalence Checking in General Resolution 14 2.7 Equivalence Checking of Circuits with Unknown CS 20 2.8 A Procedure of Equivalence Checking for Circuits with a Known CS 22 2.9 Experimental Results 23 2.10 Conclusions 26 3 Stable Sets of Points 26 3.1 Introduction 26 3.2 Stable Set of Points 28 3.3 SSP as a reachable set of points 31 3.4 Testing Satis\ufb01ability of CNF Formulas by SSP Con- struction 32 3.5 Testing Satis\ufb01ability of Symmetric CNF Formulas by SSP Construction 35 3.6 SSPs with Excluded Directions 39 3.7 Conclusions 42 v vi ADVANCED FORMAL VERIFICATION 2 Advancements in mixed BDD and SAT techniques 45 Gianpiero Cabodi and Stefano Quer 1 Introduction 45 2 Background 47 2.1 SAT Solvers 47 2.2 Binary Decision Diagrams 48 2.2.1 Zero-Suppressed Binary Decision Diagrams 49 2.2.2 Boolean Expression Diagrams 50 2.3 Model Checking and Equivalence Checking 52 3 Comparing SAT and BDD Approaches: Are they di\ufb00erent?<\/p>\n<\/blockquote>\n

This is a short excerpt from the opening of “” by Unknown, quoted for review and introduction purposes. All rights belong to the copyright holders.<\/em><\/p>\n

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