FPGA Prototyping By SystemVERILOG Examples Xilinx microBlaze MCS SoC Edition – PONG P CHU

An I/O core complying with the slot interface can be plugged into the controller and accessed by the processor. The block diagram of the MMIO subsystem is shown in Figure 11.7. Figure 11.7 Block diagram of the MMIO controller. 11.3.1 MMIO slot interface specification From the processor’s perspective, a slot is a 32-word (25-word) memory module.

The slot interface is defined as follows: addr (bus to core). It is a 5-bit address signal used to identify the 32-bit destination I/O register within the core. rd_data (core to bus). It is a 32-bit signal carrying the read data. wr_data (bus to core). It is a 32-bit signal carrying the write data. read (bus to core). It is a 1-bit control signal activated with the read operation. write (bus to core).

It is a 1-bit control signal to enable the register write. cs (bus to core). It is a 1-bit enable (i.e., “chip-select”) signal to select and activate the core. Its characteristics are similar to those of the FPro bus except that it contains a smaller five-bit address. Note that the widths of the address and data line are fixed.

The 32 registers represent the maximum number allowed in a core and some can be left unused. The 32-bit data width is selected to facilitate the processor data access. If a data item is less than 32 bits (e.g., one byte), the unused bits will be ignored. On the other hand, if a data item is more than 32 bits, it must be split into multiple registers and accessed through multiple read or write operations.

The software must pack or unpack the data as needed. An alternative to the fixed-size interface is to let each I/O core define its own address width and data width. This approach will make more efficient use of the memory space. However, because of the variation, a custom system-level decoding circuit and multiplexing circuit are needed for each individual SoC design. For simplicity, we use the fixed interface for the FPro system. 11.3.2 Basic MMIO I/O core construction Constructing an MMIO I/O cores consists of the following steps: 1.

Design the custom digital circuit. 2. Determine the I/O register map for the slot interface. 3. Derive the wrapping circuit. 4. Develop the software driver. After a custom digital circuit is developed, we need to determine how the processor interacts with the I/O core, such as writing data, reading data, retrieving status, and issuing command, and to derive a register map accordingly.

A wrapping circuit “wraps” the custom logic to create an interface compatible with the slot specification.

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Library of Congress Cataloging-in-Publication Data Names: Chu, Pong P., 1959-author. Title: FPGA prototyping by systemVERILOG examples. Xilinx MicroBlaze MCS SoC Edition / by Pong P. Chu, Cleveland State University. Description: Hoboken, NJ, USA : Wiley, 2018. | Includes bibliographical references and index. | Identifiers: LCCN 2018005487 (print) | LCCN 2018006519 (ebook) | ISBN 9781119282693 (pdf) | ISBN 9781119282709 (epub) | ISBN 9781119282662 (cloth) Subjects: LCSH: Field programmable gate arrays–Design and construction.

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